205 search results - page 37 / 41 » Clock gating architectures for FPGA power reduction |
85
Voted
EUROSYS
2008
ACM
15 years 6 months ago
2008
ACM
Non-uniform utilization of functional units in combination with hardware mechanisms such as clock gating leads to different power consumptions in different parts of a processor ch...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
65
Voted
ISSA
2004
14 years 10 months ago
2004
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
Motion estimation is a complex computation found in video compression algorithms, such as standards like MPEG-4 and H.263. This paper proposes an embedded reconfigurable array for...