205 search results - page 4 / 41 » Clock gating architectures for FPGA power reduction |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
CHES
2004
Springer
15 years 2 months ago
2004
Springer
Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to di...
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
TCAD
2010
14 years 4 months ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
ISVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...