205 search results - page 7 / 41 » Clock gating architectures for FPGA power reduction |
76
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
FPL
2004
Springer
15 years 2 months ago
2004
Springer
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell e...