205 search results - page 8 / 41 » Clock gating architectures for FPGA power reduction |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
CSB
2004
IEEE
15 years 1 months ago
2004
IEEE
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
72
Voted
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
FPL
1995
Springer
15 years 1 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...