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» Clockless IC design using handshake technology
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ASYNC
2003
IEEE
86views Hardware» more  ASYNC 2003»
13 years 11 months ago
A High-Speed Clockless Serial Link Transceiver
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
John Teifel, Rajit Manohar
CDES
2010
184views Hardware» more  CDES 2010»
13 years 4 months ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
ISPD
1998
ACM
89views Hardware» more  ISPD 1998»
13 years 10 months ago
Timing metrics for physical design of deep submicron technologies
Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit d...
Lawrence T. Pileggi
ASPDAC
2012
ACM
238views Hardware» more  ASPDAC 2012»
12 years 2 months ago
Design for manufacturability and reliability for TSV-based 3D ICs
—The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technolog...
David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Mo...