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DAC
2006
ACM
16 years 4 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
130
Voted
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
15 years 9 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
LCTRTS
2001
Springer
15 years 8 months ago
Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems
This paper presents an end-to-end synthesis technique for lowpower distributed real-time system design. This technique synthesizes supply voltages of resources to optimize system-...
Dong-In Kang, Stephen P. Crago, Jinwoo Suh
DAC
2006
ACM
16 years 4 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
127
Voted
EMO
2006
Springer
158views Optimization» more  EMO 2006»
15 years 7 months ago
The Hypervolume Indicator Revisited: On the Design of Pareto-compliant Indicators Via Weighted Integration
The design of quality measures for approximations of the Pareto-optimal set is of high importance not only for the performance assessment, but also for the construction of multiobj...
Eckart Zitzler, Dimo Brockhoff, Lothar Thiele