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128
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DAC
1994
ACM
15 years 7 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar
120
Voted
EOR
2008
112views more  EOR 2008»
15 years 3 months ago
DEA based auctions
We discuss the design of multi-dimensional tender and auction mechanisms that combine Data Envelopment Analysis (DEA) and auction theory. The mechanisms select an agent to perform...
Peter Bogetoft, Kurt Nielsen
125
Voted
TIP
2008
79views more  TIP 2008»
15 years 3 months ago
An Overview and Performance Evaluation of Classification-Based Least Squares Trained Filters
An overview of the classification-based least squares trained filters on picture quality improvement algorithms is presented. For each algorithm, the training process is unique and...
Ling Shao, Hui Zhang, Gerard de Haan
140
Voted
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
15 years 10 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
149
Voted
TCAD
2008
136views more  TCAD 2008»
15 years 3 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar