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135
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DAC
2005
ACM
15 years 5 months ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
113
Voted
ISSAC
2007
Springer
111views Mathematics» more  ISSAC 2007»
15 years 9 months ago
Numerical optimization in hybrid symbolic-numeric computation
Approximate symbolic computation problems can be formulated as constrained or unconstrained optimization problems, for example: GCD [3, 8, 12, 13, 23], factorization [5, 10], and ...
Lihong Zhi
148
Voted
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
16 years 4 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
124
Voted
DAC
2006
ACM
16 years 4 months ago
Optimality study of resource binding with multi-Vdds
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
126
Voted
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 8 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...