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129
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EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
15 years 7 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
DAC
1999
ACM
16 years 4 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
ICRA
2009
IEEE
118views Robotics» more  ICRA 2009»
15 years 10 months ago
Design and implementation of a 9-axis inertial measurement unit
— We report on a 9-axis inertial measurement unit (IMU) which utilizes 3-axis angular velocity measurements from rate gyros and 6-axis linear acceleration measurements from three...
Pei-Chun Lin, Chi-Wei Ho
139
Voted
VTC
2008
IEEE
113views Communications» more  VTC 2008»
15 years 10 months ago
On Design of TDD for Joint Uplink and Downlink Resource Allocation in OFDMA-Based WiMax
— In this paper, we study the joint design of uplink and downlink resources in OFDMA-based systems. We first analyze the interactions between uplink and downlink, due essentiall...
Tijani Chahed, Salah-Eddine Elayoubi, Eitan Altman
121
Voted
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
15 years 9 months ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...