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ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram
EWSN
2004
Springer
16 years 3 months ago
Design of Surveillance Sensor Grids with a Lifetime Constraint
A surveillance area is to be monitored using a grid network of heterogeneous sensor nodes. There are two types of nodes; type 0 nodes which perform sensing and relaying of data wit...
Vivek Mhatre, Catherine Rosenberg, Daniel Kofman, ...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
16 years 1 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
ASAP
2006
IEEE
168views Hardware» more  ASAP 2006»
15 years 8 months ago
Dual-Processor Design of Energy Efficient Fault-Tolerant System
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
Shaoxiong Hua, Pushkin R. Pari, Gang Qu
CORR
2010
Springer
140views Education» more  CORR 2010»
15 years 4 months ago
Performance Bounds and Design Criteria for Estimating Finite Rate of Innovation Signals
In this paper, we consider the problem of estimating finite rate of innovation (FRI) signals from noisy measurements, and specifically analyze the interaction between FRI technique...
Zvika Ben-Haim, Tomer Michaeli, Yonina C. Eldar