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ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
16 years 1 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
15 years 10 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
15 years 8 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
JCIT
2008
129views more  JCIT 2008»
15 years 4 months ago
An Enhanced tree based MAODV Protocol for MANETs using Genetic Algorithm
Multicast routing protocols in Mobile Ad-hoc Networks (MANETs) are emerging for wireless group communication which includes application such as multipoint data dissemination and m...
E. Baburaj, V. Vasudevan
EURODAC
1994
IEEE
139views VHDL» more  EURODAC 1994»
15 years 8 months ago
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
: This paper presents an approach to high-level synthesis which is based upon a 0/1 integer programming model. In contrast to other approaches, this model allows solving all three ...
Birger Landwehr, Peter Marwedel, Rainer Dömer