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ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
PE
2006
Springer
127views Optimization» more  PE 2006»
14 years 10 months ago
Design and analysis of a class-aware recursive loop scheduler for class-based scheduling
In this paper, we consider the problem of devising a loop scheduler that allocates slots to users according to their relative weights as smoothly as possible. Instead of the exist...
Raphael Rom, Moshe Sidi, Hwee Pink Tan
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
15 years 4 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...
SAMOS
2004
Springer
15 years 3 months ago
DIF: An Interchange Format for Dataflow-Based Design Tools
The dataflow interchange format (DIF) is a textual language that is geared towards capturing the semantics of graphical design tools for DSP system design. A key objective of DIF i...
Chia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz ...
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
15 years 4 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky