Sciweavers

169 search results - page 13 / 34
» Co-Scheduling Hardware and Software Pipelines
Sort
View
105
Voted
INTEGRATION
2007
100views more  INTEGRATION 2007»
15 years 1 months ago
A fast pipelined multi-mode DES architecture operating in IP representation
The Data Encryption Standard (DES) is a cipher that is still used in a broad range of applications, from smartcards, where it is often implemented as a tamperresistant embedded co...
Sylvain Guilley, Philippe Hoogvorst, Renaud Pacale...
IEEEPACT
2007
IEEE
15 years 8 months ago
Unified Architectural Support for Soft-Error Protection or Software Bug Detection
In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically...
Martin Dimitrov, Huiyang Zhou
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 8 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
SIGCOMM
2010
ACM
15 years 2 months ago
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
We present SwitchBlade, a platform for rapidly deploying custom protocols on programmable hardware. SwitchBlade uses a pipeline-based design that allows individual hardware module...
Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad M...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 5 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...