169 search results - page 15 / 34 » Co-Scheduling Hardware and Software Pipelines |
157
Voted
FPGA
2010
ACM
15 years 2 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
128
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
109
Voted
MICRO
1995
IEEE
15 years 5 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
116
Voted
HPCA
2011
IEEE
14 years 5 months ago
2011
IEEE
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
118
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ICCD
1995
IEEE
15 years 5 months ago
1995
IEEE
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of through...