Sciweavers

169 search results - page 20 / 34
» Co-Scheduling Hardware and Software Pipelines
Sort
View
98
Voted
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
15 years 10 months ago
In-Line Interrupt Handling for Software-Managed TLBs
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
Aamer Jaleel, Bruce L. Jacob
138
Voted
BMCBI
2010
153views more  BMCBI 2010»
15 years 1 months ago
Pash 3.0: A versatile software package for read mapping and integrative analysis of genomic and epigenomic variation using massi
Background: Massively parallel sequencing readouts of epigenomic assays are enabling integrative genome-wide analyses of genomic and epigenomic variation. Pash 3.0 performs sequen...
Cristian Coarfa, Fuli Yu, Christopher A. Miller, Z...
111
Voted
MICRO
2006
IEEE
114views Hardware» more  MICRO 2006»
15 years 7 months ago
Authentication Control Point and Its Implications For Secure Processor Design
Secure processor architecture enables tamper-proof protection on software that addresses many difficult security problems such as reverse-engineering prevention, trusted computing...
Weidong Shi, Hsien-Hsin S. Lee
CHES
1999
Springer
91views Cryptology» more  CHES 1999»
15 years 6 months ago
A High-Performance Flexible Architecture for Cryptography
Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementat...
R. Reed Taylor, Seth Copen Goldstein
CF
2007
ACM
15 years 5 months ago
An analysis of the effects of miss clustering on the cost of a cache miss
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
Thomas R. Puzak, Allan Hartstein, Philip G. Emma, ...