169 search results - page 21 / 34 » Co-Scheduling Hardware and Software Pipelines |
153
Voted
SBCCI
2005
ACM
15 years 7 months ago
2005
ACM
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
215
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CSE
2011
IEEE
14 years 1 months ago
2011
IEEE
— In network based applications, packet capture is the main area that attracts many researchers in developing traffic monitoring systems. Along with the packet capture, many othe...
166
Voted
HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
ICMCS
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
97
Voted
CODES
2002
IEEE
15 years 6 months ago
2002
IEEE
Eclipse defines a heterogeneous multiprocessor architecture template for data-dependent stream processing. Intended as a scalable and flexible subsystem of forthcoming media-proce...