169 search results - page 24 / 34 » Co-Scheduling Hardware and Software Pipelines |
104
Voted
CODES
2005
IEEE
15 years 7 months ago
2005
IEEE
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
150
Voted
LCTRTS
2000
Springer
15 years 5 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
128
Voted
CGO
2004
IEEE
15 years 5 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
184
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CF
2011
ACM
14 years 1 months ago
2011
ACM
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
119
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CASES
2007
ACM
15 years 5 months ago
2007
ACM
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...