169 search results - page 27 / 34 » Co-Scheduling Hardware and Software Pipelines |
102
Voted
IPPS
2000
IEEE
15 years 6 months ago
2000
IEEE
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
119
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LCTRTS
1998
Springer
15 years 6 months ago
1998
Springer
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
105
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CASES
2008
ACM
15 years 3 months ago
2008
ACM
In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function ...
120
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
121
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CASES
2010
ACM
14 years 12 months ago
2010
ACM
Mobile computing platforms in the form of smart phones, netbooks, and personal digital assistants have become an integral part of our everyday lives. Moving ahead to the future, m...