169 search results - page 30 / 34 » Co-Scheduling Hardware and Software Pipelines |
123
Voted
CODES
2008
IEEE
15 years 8 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
121
Voted
HIPEAC
2007
Springer
15 years 8 months ago
2007
Springer
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
142
Voted
CGO
2003
IEEE
15 years 7 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
124
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CASES
2003
ACM
15 years 7 months ago
2003
ACM
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the po...
104
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...