169 search results - page 33 / 34 » Co-Scheduling Hardware and Software Pipelines |
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
ASPLOS
2010
ACM
15 years 4 months ago
2010
ACM
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
89
Voted
ACSC
2006
IEEE
15 years 3 months ago
2006
IEEE
Interactive virtual reality requires at least 60 frames per second in order to ensure smooth motion. For a good immersive experience, it is also necessary to have low end-to-end l...
88
Voted
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...