169 search results - page 5 / 34 » Co-Scheduling Hardware and Software Pipelines |
MICRO
1997
IEEE
15 years 3 months ago
1997
IEEE
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
106
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ICCAD
2001
IEEE
15 years 8 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ISSS
2000
IEEE
15 years 3 months ago
2000
IEEE
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
104
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CF
2005
ACM
15 years 1 months ago
2005
ACM
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...