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» Co-Scheduling Hardware and Software Pipelines
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CVPR
2007
IEEE
16 years 1 months ago
OpenVL: Towards A Novel Software Architecture for Computer Vision
This paper presents our progress on OpenVL - a novel software architecture to address efficiency through facilitating hardware acceleration, reusability and scalability for comput...
Changsong Shen, S. Sidney Fels, James J. Little
CGO
2009
IEEE
15 years 6 months ago
Software Pipelined Execution of Stream Programs on GPUs
—The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. This model allows programmers to sp...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
SCOPES
2005
Springer
15 years 5 months ago
Generic Software Pipelining at the Assembly Level
Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the co...
Daniel Kästner, Markus Pister
TVLSI
2008
115views more  TVLSI 2008»
14 years 11 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
DATE
2007
IEEE
139views Hardware» more  DATE 2007»
15 years 6 months ago
Efficient high-performance ASIC implementation of JPEG-LS encoder
- This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The prop...
Markos Papadonikolakis, Vasilleios Pantazis, Athan...