47 search results - page 4 / 10 » Co-design of interleaved memory systems |
ASAP
2008
IEEE
13 years 8 months ago
2008
IEEE
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
DELTA
2008
IEEE
13 years 8 months ago
2008
IEEE
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
SAMOS
2007
Springer
14 years 11 days ago
2007
Springer
In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address ...
TIP
1998
13 years 5 months ago
1998
Abstract— This correspondence addresses the use of a joint sourcechannel coding strategy for enhancing the error resilience of images transmitted over a binary channel with addit...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...