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CASES
2009
ACM
15 years 4 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
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EMSOFT
2006
Springer
15 years 1 months ago
A hierarchical coordination language for interacting real-time tasks
We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the la...
Arkadeb Ghosal, Alberto L. Sangiovanni-Vincentelli...
RTAS
1998
IEEE
15 years 1 months ago
Performance Analysis of an RSVP-Capable Router
RSVP is a bandwidth reservation protocol that allows distributed real-time applications such as video-conferencing software to make bandwidth reservations over packetswitched netw...
Tzi-cker Chiueh, Anindya Neogi, Paul A. Stirpe
MOBICOM
2012
ACM
13 years 1 days ago
Distinguishing users with capacitive touch communication
As we are surrounded by an ever-larger variety of post-PC devices, the traditional methods for identifying and authenticating users have become cumbersome and time-consuming. In t...
Tam Vu, Akash Baid, Simon Gao, Marco Gruteser, Ric...
CASES
2007
ACM
15 years 1 months ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula