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TVLSI
2008
187views more  TVLSI 2008»
14 years 11 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 8 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
15 years 3 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
PDPTA
2000
15 years 1 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...
FPL
2008
Springer
111views Hardware» more  FPL 2008»
15 years 1 months ago
Hyperreconfigurable architectures
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increa...
Sebastian Lange, Martin Middendorf