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CODES
2006
IEEE
14 years 11 months ago
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buff...
Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, ...
CODES
2005
IEEE
15 years 3 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
CODES
2001
IEEE
15 years 1 months ago
Dynamic I/O power management for hard real-time systems
Power consumption is an important design parameter for embedded and portable systems. Software-controlled (or dynamic) power management (DPM) has recently emerged as an attractive...
Vishnu Swaminathan, Krishnendu Chakrabarty, S. Sit...
SAC
2008
ACM
14 years 9 months ago
A self-balancing striping scheme for NAND-flash storage systems
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
Yu-Bin Chang, Li-Pin Chang
CODES
2000
IEEE
15 years 2 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf