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» Code Compression for Embedded Systems
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DATE
2007
IEEE
99views Hardware» more  DATE 2007»
15 years 4 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
ERSA
2008
93views Hardware» more  ERSA 2008»
14 years 11 months ago
Multiparadigm Computing for Space-Based Synthetic Aperture Radar
Projected computational requirements for future space missions are outpacing technologies and trends in conventional embedded microprocessors. In order to meet the necessary levels...
Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, A...
ATS
2010
IEEE
239views Hardware» more  ATS 2010»
14 years 5 months ago
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
Michael A. Kochte, Christian G. Zoellin, Rafal Bar...
DCC
2002
IEEE
15 years 9 months ago
PPMexe: PPM for Compressing Software
With the emergence of software delivery platforms such as Microsoft's .NET, code compression has become one of the core enabling technologies strongly affecting system perfor...
Milenko Drinic, Darko Kirovski
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra