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CASES
2004
ACM
15 years 1 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
ASPLOS
1989
ACM
15 years 1 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
15 years 1 months ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
ICMCS
2006
IEEE
130views Multimedia» more  ICMCS 2006»
15 years 3 months ago
Video Analysis and Compression on the STI Cell Broadband Engine Processor
With increased concern for physical security, video surveillance is becoming an important business area. Similar camera-based system can also be used in such diverse applications ...
Lurng-Kuo Liu, Sreeni Kesavarapu, Jonathan Connell...
CGO
2008
IEEE
15 years 3 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic