79 search results - page 4 / 16 » Code Compression for VLIW Processors Using Variable-to-Fixed... |
116
Voted
MICRO
2000
IEEE
15 years 28 days ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
111
Voted
CASES
2007
ACM
15 years 5 months ago
2007
ACM
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
107
Voted
ASAP
2006
IEEE
15 years 4 months ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
119
Voted
ICCAD
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
129
Voted
CODES
2004
IEEE
15 years 4 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...