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116
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ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
15 years 9 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
112
Voted
KBSE
2008
IEEE
15 years 7 months ago
Type-Checking Software Product Lines - A Formal Approach
—A software product line (SPL) is an efficient means to generate a family of program variants for a domain from a single code base. However, because of the potentially high numb...
Christian Kästner, Sven Apel
92
Voted
CC
2005
Springer
124views System Software» more  CC 2005»
15 years 6 months ago
Boosting the Performance of Multimedia Applications Using SIMD Instructions
Modern processors’ multimedia extensions (MME) provide SIMD ISAs to boost the performance of typical operations in multimedia applications. However, automatic vectorization suppo...
Weihua Jiang, Chao Mei, Bo Huang, Jianhui Li, Jiah...
93
Voted
ICC
2000
IEEE
15 years 5 months ago
A Class of Block-Iterative Equalizers for Intersymbol Interference Channels
—A new and efficient class of nonlinear equalizers is developed for intersymbol interference (ISI) channels. These “iterated-decision equalizers” use an optimized multipass a...
Albert M. Chan, Gregory W. Wornell
DAC
1997
ACM
15 years 5 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider