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101
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ICS
2001
Tsinghua U.
15 years 5 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
16 years 1 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
88
Voted
ICMCS
2007
IEEE
120views Multimedia» more  ICMCS 2007»
15 years 7 months ago
Optimal Scheduling of Media Packets with Multiple Distortion Measures
Due to the increase in diversity of wireless devices, streaming media systems must be capable of serving multiple types of users. Scalable coding allows for adaptations without re...
Carri W. Chan, Nicholas Bambos, Susie Wee, John G....
101
Voted
ADAEUROPE
2007
Springer
15 years 7 months ago
Towards User-Level Extensibility of an Ada Library: An Experiment with Cheddar
In this article, we experiment a way to extend an Ada library called Cheddar. Cheddar provides a domain specific language. Programs written with this domain specific language can...
Frank Singhoff, Alain Plantec
FPL
2007
Springer
124views Hardware» more  FPL 2007»
15 years 6 months ago
A Quantitative Prediction Model for Hardware/Software Partitioning
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Ga...