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ICPPW
2002
IEEE
15 years 9 months ago
Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
Jaume Abella, Antonio González, Josep Llosa...
ICASSP
2011
IEEE
14 years 8 months ago
Broadband direction estimation method utilizing combined pressure and energy gradients from optimized microphone array
This paper proposes a method for analyzing the direction of the arrival of sound by estimating the sound intensity vector from the pressure and energy gradients of closely-spaced ...
Jukka Ahonen, Ville Pulkki
ARITH
2009
IEEE
15 years 11 months ago
Datapath Synthesis for Standard-Cell Design
Datapath synthesis for standard-cell design goes through extraction of arithmetic operations from RTL code, high-level arithmetic optimizations and netlist generation. Numerous ar...
Reto Zimmermann
ICESS
2007
Springer
15 years 10 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
GECCO
2003
Springer
111views Optimization» more  GECCO 2003»
15 years 9 months ago
An Adaptive Penalty Scheme for Steady-State Genetic Algorithms
A parameter-less adaptive penalty scheme for steady-state genetic algorithms applied to constrained optimization problems is proposed. For each constraint, a penalty parameter is a...
Helio J. C. Barbosa, Afonso C. C. Lemonge