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GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 8 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
109
Voted
ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
15 years 8 months ago
Phase Tracking and Prediction
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...
Timothy Sherwood, Suleyman Sair, Brad Calder
120
Voted
ISPASS
2003
IEEE
15 years 8 months ago
An MPEG-4 performance study for non-SIMD, general purpose architectures
MPEG-4 is an important international standard with wide applicability. This paper focuses on MPEG-4’s main profile, video, whose approach allows more efficiency in coding and ...
Sally A. McKee, Zhen Fang, Mateo Valero
119
Voted
PLDI
2003
ACM
15 years 8 months ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
127
Voted
IEEEPACT
2002
IEEE
15 years 7 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall