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» Code compression for low power embedded system design
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DAC
2005
ACM
14 years 11 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 1 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
HOTI
2008
IEEE
15 years 4 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
EUROSYS
2010
ACM
15 years 6 months ago
Reverse Engineering of Binary Device Drivers with RevNIC
This paper presents a technique that helps automate the reverse engineering of device drivers. It takes a closed-source binary driver, automatically reverse engineers the driverâ€...
Vitaly Chipounov, George Candea