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146
Voted
ICS
1994
Tsinghua U.
15 years 8 months ago
1994
Tsinghua U.
We present a parallel code generation algorithm for complete applications and a new experimental methodology that tests the efficacy of our approach. The algorithm optimizes for d...
124
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ASPDAC
2007
ACM
15 years 8 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
132
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CODES
2004
IEEE
15 years 7 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
131
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CODES
2004
IEEE
15 years 7 months ago
2004
IEEE
Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and map...
136
Voted
CODES
2004
IEEE
15 years 7 months ago
2004
IEEE
Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs trad...