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» Code restructuring for improving cache performance of MPSoCs
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135
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IEEEPACT
2009
IEEE
14 years 11 months ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...
121
Voted
MICRO
2005
IEEE
107views Hardware» more  MICRO 2005»
15 years 6 months ago
Stream Programming on General-Purpose Processors
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
Jayanth Gummaraju, Mendel Rosenblum
103
Voted
EUROPAR
2010
Springer
15 years 2 months ago
Multithreaded Geant4: Semi-automatic Transformation into Scalable Thread-Parallel Software
This work presents an application case study. Geant4 is a 750,000 line toolkit first designed in the mid-1990s and originally intended only for sequential computation. Intel's...
Xin Dong 0004, Gene Cooperman, John Apostolakis
130
Voted
CASES
2003
ACM
15 years 6 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
105
Voted
CODES
1998
IEEE
15 years 5 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...