151 search results - page 3 / 31 » Code transformation strategies for extensible embedded proce... |
104
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CODES
2001
IEEE
15 years 3 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
ICIP
2000
IEEE
16 years 1 months ago
2000
IEEE
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
SAC
2005
ACM
15 years 5 months ago
2005
ACM
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
118
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ISHPC
2003
Springer
15 years 4 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...