27 search results - page 1 / 6 » Code-coverage Based Test Vector Generation for SystemC Desig... |
124
Voted
ISVLSI
2007
IEEE
15 years 9 months ago
2007
IEEE
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
149
Voted
FDL
2007
IEEE
15 years 10 months ago
2007
IEEE
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
135
Voted
ICCAD
1996
IEEE
15 years 7 months ago
1996
IEEE
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
113
Voted
DDECS
2007
IEEE
15 years 5 months ago
2007
IEEE
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...
174
Voted
GLVLSI
2009
IEEE
15 years 1 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...