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ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
15 years 11 months ago
On-Line Histogram Equalization for Flash ADC
— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.3...
Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire
APSEC
2006
IEEE
15 years 11 months ago
Testing of Timer Function Blocks in FBD
Testing for time-related behaviors of PLC software is important and should be performed carefully. We propose a structural testing technique on Function Block Diagram(FBD) network...
Eunkyoung Jee, Seungjae Jeon, Hojung Bang, Sung De...
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
15 years 11 months ago
A Graph Based Algorithm for Data Path Optimization in Custom Processors
The rising complexity, customization and short time to market of modern digital systems requires automatic methods for generation of high performance architectures for such system...
Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, ...
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ICMCS
2006
IEEE
130views Multimedia» more  ICMCS 2006»
15 years 11 months ago
Video Analysis and Compression on the STI Cell Broadband Engine Processor
With increased concern for physical security, video surveillance is becoming an important business area. Similar camera-based system can also be used in such diverse applications ...
Lurng-Kuo Liu, Sreeni Kesavarapu, Jonathan Connell...
LCTRTS
2005
Springer
15 years 10 months ago
Probabilistic source-level optimisation of embedded programs
Efficient implementation of DSP applications is critical for many embedded systems. Optimising C compilers for embedded processors largely focus on code generation and instructio...
Björn Franke, Michael F. P. O'Boyle, John Tho...