62 search results - page 7 / 13 » Combinational equivalence checking for threshold logic circu... |
124
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CONCUR
2006
Springer
15 years 1 months ago
2006
Springer
Propositional temporal logic is not suitable for expressing properties on the evolution of dynamically allocated entities over time. In particular, it is not possible to trace such...
111
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DAC
2003
ACM
16 years 17 days ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
ARITH
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper we investigate the implementation of basic arithmetic functions, such as addition and multiplication, in Single Electron Tunneling (SET) technology. First, we descri...
109
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IPL
2007
14 years 11 months ago
2007
A new algorithm is presented for testing if a regular language is locally threshold testable. The new algorithm is slower than existing algorithms, but its correctness proof is sh...
ICCAD
1997
IEEE
15 years 3 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...