62 search results - page 9 / 13 » Combinational equivalence checking for threshold logic circu... |
APN
2008
Springer
14 years 11 months ago
2008
Springer
Model checking is a powerful and widespread technique for the verification of finite distributed systems. However, the main hindrance for wider application of this technique is the...
CDES
2006
14 years 11 months ago
2006
Multi-valued Fredkin gates (MVFG) are reversible gates and they can be considered as modified version of the better known reversible gate the Fredkin gate. Reversible logic gates ...
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...