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RTAS
1997
IEEE
15 years 2 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
SC
1992
ACM
15 years 1 months ago
Willow: A Scalable Shared Memory Multiprocessor
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
John K. Bennett, Sandhya Dwarkadas, Jay A. Greenwo...
CASES
2006
ACM
15 years 1 months ago
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
Won So, Alexander G. Dean
GECCO
2006
Springer
195views Optimization» more  GECCO 2006»
15 years 1 months ago
Studying XCS/BOA learning in Boolean functions: structure encoding and random Boolean functions
Recently, studies with the XCS classifier system on Boolean functions have shown that in certain types of functions simple crossover operators can lead to disruption and, conseque...
Martin V. Butz, Martin Pelikan
IIWAS
2003
14 years 11 months ago
Zero-Latency Data Warehousing for Heterogeneous Data Sources and Continuous Data Streams
In this paper, a framework for building an overall Zero-Latency Data Warehouse system (ZLDWH) is provided. Such a ZLDWH requires tasks such as data changes detection, continuous l...
Tho Manh Nguyen, A. Min Tjoa