Pure Pattern Type Systems (P2 TS) combine in a unified setting the capabilities of rewriting and λ-calculus. Their type systems, adapted from Barendregt’s λ-cube, are especial...
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
We describe WEST, a WEb browser for Small Terminals, that aims to solve some of the problems associated with accessing web pages on hand-held devices. Through a novel combination ...
This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. Th...
This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates...
Mary W. Hall, Saman P. Amarasinghe, Brian R. Murph...