111 search results - page 7 / 23 » Combining Optimism Limiting Schemes in Time Warp Based Paral... |
JCO
2011
14 years 6 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
99
Voted
SASP
2009
IEEE
15 years 6 months ago
2009
IEEE
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
100
Voted
ISCI
2007
14 years 11 months ago
2007
Declustering techniques reduce query response time through parallel I/O by distributing data among multiple devices. Except for a few cases it is not possible to find declusterin...
PPL
2008
14 years 11 months ago
2008
This paper investigates the influence of the interconnection network topology of a parallel system on the delivery time of an ensemble of messages, called the communication scheme...
GLOBECOM
2007
IEEE
15 years 6 months ago
2007
IEEE
— Over the last years, the Internet has evolved towards becoming the dominant platform for deploying real time and multimedia services. This evolution has had as a consequence th...