Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
Ted Huffmire, Timothy E. Levin, Michael Bilzor, Cy...
The need for incremental constraint maintenance within collections of semi-structured documents has been ever increasing in the last years due to the widespread diffusion of XML. T...
This paper formulates and illustrates the integration of resource safety verification into a design methodology for development of verified and robust real-time embedded systems. ...
Jianliang Yi, Honguk Woo, James C. Browne, Aloysiu...
To support planning of massive transportations under time-critical conditions, in particular, evacuation of people from a disasteraffected area, we have developed a software modul...
Gennady L. Andrienko, Natalia V. Andrienko, Ulrich...