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» Combining Software and Hardware Verification Techniques
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DATE
2009
IEEE
115views Hardware» more  DATE 2009»
15 years 5 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
CODES
2006
IEEE
15 years 8 months ago
A run-time, feedback-based energy estimation model For embedded devices
We present an adaptive, feedback-based, energy estimation model for battery-powered embedded devices such as sensor network gateways and hand-held computers. Our technique maps ha...
Selim Gurun, Chandra Krintz
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
15 years 7 months ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
NSDI
2004
15 years 3 months ago
Model Checking Large Network Protocol Implementations
Network protocols must work. The effects of protocol specification or implementation errors range from reduced performance, to security breaches, to bringing down entire networks....
Madanlal Musuvathi, Dawson R. Engler
MEMOCODE
2010
IEEE
14 years 11 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler