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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
15 years 1 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
112
Voted
CASES
2007
ACM
15 years 5 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
100
Voted
LCPC
2005
Springer
15 years 7 months ago
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Ro...
104
Voted
SARA
2009
Springer
15 years 8 months ago
Automated Redesign with the General Redesign Engine
: Given a system design (SD), a key task is to optimize this design to reduce the probability of catastrophic failures. We consider the task of redesigning an SD to minimize the pr...
Alexander Feldman, Gregory M. Provan, Johan de Kle...
ACSC
2006
IEEE
15 years 8 months ago
Rendering multi-perspective images with trilinear projection
Non-linear projections of 3D graphical scenes can be used to compute reflections and refractions in curved surfaces, draw artistic images in the style of Escher or Picasso, and p...
Scott Vallance, Paul R. Calder