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» Combining Software and Hardware Verification Techniques
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ISPASS
2010
IEEE
15 years 4 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
CODES
2005
IEEE
15 years 3 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
SIGMETRICS
2005
ACM
110views Hardware» more  SIGMETRICS 2005»
15 years 3 months ago
Empirical evaluation of multi-level buffer cache collaboration for storage systems
To bridge the increasing processor-disk performance gap, buffer caches are used in both storage clients (e.g. database systems) and storage servers to reduce the number of slow di...
Zhifeng Chen, Yan Zhang, Yuanyuan Zhou, Heidi Scot...
DAC
2010
ACM
15 years 1 months ago
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...
Albert Cohen, Erven Rohou
MAM
2007
157views more  MAM 2007»
14 years 9 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene