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» Combining optimizations in automated low power design
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ICCAD
2001
IEEE
106views Hardware» more  ICCAD 2001»
15 years 6 months ago
A Layout-Aware Synthesis Methodology for RF Circuits
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
Peter J. Vancorenland, Geert Van der Plas, Michiel...
DAC
2009
ACM
15 years 10 months ago
Dynamic thermal management via architectural adaptation
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
Ramkumar Jayaseelan, Tulika Mitra
IESS
2007
Springer
128views Hardware» more  IESS 2007»
15 years 4 months ago
An Interactive Design Environment for C-based High-Level Synthesis
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
INFOCOM
2010
IEEE
14 years 8 months ago
Joint Power and Secret Key Queue Management for Delay Limited Secure Communication
—In recent years, the famous wiretap channel has been revisited by many researchers and information theoretic secrecy has become an active area of research in this setting. In th...
Onur Güngör 0002, Jian Tan, Can Emre Kok...
CDES
2006
158views Hardware» more  CDES 2006»
14 years 11 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia