Sciweavers

838 search results - page 106 / 168
» Combining optimizations in automated low power design
Sort
View
FDL
2008
IEEE
15 years 4 months ago
Model-based Design Space Exploration for RTES with SysML and MARTE
The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Tim...
Marcello Mura, Luis Gabriel Murillo, Mauro Prevost...
DAC
2004
ACM
15 years 10 months ago
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
The desynchronization approach combines a traditional synchronous specification style with a robust asynchronous implementation model. The main contribution of this paper is the d...
Abhijit Davare, Kelvin Lwin, Alex Kondratyev, Albe...
HPCA
2009
IEEE
15 years 10 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
DAC
2008
ACM
15 years 10 months ago
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array fo
: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRA...
Jing Li, Charles Augustine, Sayeef S. Salahuddin, ...
DAC
2007
ACM
15 years 10 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...